More

    Infineon launches new OptiMOS™ power MOSFET package enables innovative Source-Down technology

    OptiMOS™ Source-Down Power MOSFET
    OptiMOS™ Source-Down Power MOSFET

    High power density, optimized performance, and ease of use are key requirements when designing modern power systems. To offer practical solutions for design challenges in end applications, Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) launches the new generation of OptiMOS™ Source-Down (SD) power MOSFETs. They come in a PQFN 3.3 x 3.3 mm 2 package and a wide voltage class ranging from 25 V up to 100 V. This package sets a new standard in power MOSFET performance, offering higher efficiency, higher power density, superior thermal management and low bill-of-material (BOM). The PQFN addresses applications including motor drives, SMPS for server and telecom and OR-ing, as well as battery management systems.

    Compared to the standard Drain-Down concept, the latest Source-Down package technology enables a larger silicon die in the same package outline. In addition, the losses contributed by the package, limiting the overall performance of the device, can be reduced. This enables a reduction in RDS(on) by up to 30 percent compared to the state of the art Drain-Down package. The benefit at the system level is a shrink in the form factor with the possibility to move from a SuperSO8 5 x 6 mm 2 footprint to a PQFN 3.3 x 3.3 mm 2 package with a space reduction of about 65 percent. This allows for the available space to be used more effectively, enhancing the power density and system efficiency in the end system.

    Additionally, in the Source-Down concept, the heat is dissipated directly into the PCB through a thermal pad instead of over the bond wire or the copper clip. This improves the thermal resistance R thJC by more than 20 percent, from 1.8 K/W down to 1.4 K/W, thus enabling simplified thermal management. Infineon offers two different footprint versions and layout options: the SD Standard-Gate and the SD Center-Gate. The Standard-Gate layout simplifies the drop-in replacement of Drain-Down packages, while the Center-Gate layout enables optimized and easier parallelization. These two options can bring optimal device arrangement in the PCB, optimized PCB parasitics, and ease of use.

    OptiMOS™ Source-Down power MOSFETs are now available in PQFN 3.3 x 3.3 mm 2 packaging, a wide range of voltage classes from 25 up to 100 V, and two different footprint versions. More information is available at www.infineon.com/source-down.

    아이씨엔매거진
    ASI
    오승모 기자
    오승모 기자http://icnweb.kr
    기술로 이야기를 만드는 "테크 스토리텔러". 아이씨엔 미래기술센터 수석연구위원이며, 아이씨엔매거진 편집장을 맡고 있습니다. 디지털 전환을 위한 데이터에 기반한 혁신 기술들을 국내 엔지니어들에게 쉽게 전파하는데 노력하는 중입니다.
    • AW2025
    • Mobile World Live
    • 파스텍 배너 900
    • hilscher
    ASI

    Join our Newsletter

    Get the latest newsletters on industry innovations.

    AW2025
    MWC
    오토모션
    semicon 2025
    embeddedworld 2025
    Hannover messe

    Related articles

    넥스페리아, JEDEC 표준 구리 클립 CCPAK1212 패키지를 MOSFET 적용

    넥스페리아가 JEDEC 표준화 규정에 등록된 구리 클립 CCPAK1212 패키지를 MOSFET에 적용했다

    넥스페리아, 자동차용 120V/4A 하프 브리지 게이트 드라이버 출시

    넥스페리아가 채널간 지연 시간이 짧은 고성능 하프 브리지 게이트 드라이버를 출시했다

    넥스페리아, 자동차 등급 인증 소신호 MOSFET 신규 출시

    넥스페리아가 소형 DFN 패키지의 단일 및 이중 소신호 MOSFET제품들을 출시했다고 전했다

    기자의 추가 기사

    IIoT

    오토모션
    Hannover messe

    추천 기사

    mobility