Altera Corporation today dramatically simplified a programmer’s ability to accelerate algorithms in FPGAs. The Altera SDK for OpenCL version 14.0 includes a programmer-familiar rapid prototyping design flow that enables users to prototype designs in minutes on an FPGA accelerator board. Altera, along with its board partners, further accelerate the development of FPGA-based applications by offering reference designs, reference platforms and FPGA development boards that are supported by Altera’s OpenCL solution. These reference platforms also streamline the development of custom FPGA accelerators to meet specific application requirements.

Altera is the only company to offer a publicly available, OpenCL conformant software development kit (SDK). The solution allows programmers to develop algorithms with the C-based OpenCL language and harness the performance and power efficiencies of FPGAs. A rapid prototyping design flow included in the Altera SDK for OpenCL version 14.0 allows OpenCL kernel code to be emulated, debugged, optimized, profiled and re-compiled to a hardware implementation in minutes. The re-compiled kernels can be tested and run on an FPGA immediately, saving programmers weeks of development time.

Altera and its board partners further simplify the experience of getting applications up and running using FPGA accelerators by offering a broad selection of Altera-developed reference platforms, reference designs and FPGA accelerator boards. Altera provides a variety of design examples that demonstrate how to describe applications in OpenCL, including OPRA FAST Parser for finance applications, JPEG decoder for big data applications and video downscaling for video applications.

Design teams that want to create custom solutions that feature a unique set of peripherals can create their own custom FPGA accelerators and save significant development time by using Altera-developed reference platforms. The reference platforms include an SoC platform for embedded applications, a high-performance computing (HPC) platform and a low-latency network enabled platform which utilizes IO Channels.

Additional enhancements made to the Altera SDK for OpenCL version 14.0 include:
•Production support for IO Channels that allow streaming data into and out of the FPGA as well as kernel channels allowing the result reuse from one kernel to another in a hardware pipeline for significantly higher performance and throughput with little to no host and memory interaction.
•Production support for single-chip SoC solutions (Cyclone V SoC and Arria V SoC), where the host is an embedded ARM core processor integrated in the FPGA accelerator.

About the Altera SDK for OpenCL

Altera’s SDK for OpenCL allows programmers to take OpenCL code and rapidly exploit the massively parallel architecture of an FPGA. Programmers targeting FPGAs achieve higher performance at significantly lower power compared to alternative hardware architectures, such as GPUs and CPUs. On average, FPGAs deliver higher performance at one-fifth the power of a GPU. Altera’s OpenCL solutions are supported by third-party boards through the Altera Preferred Board Partner Program for OpenCL. Visit www.altera.com/opencl.

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